Physical Design Engineer

TAA Solutions is looking for a Physical Design Engineer to support one of their clients that is based out in Phoenix, AZ. We are looking for a strong Engineer to provide design verification services for multi CPU/DSP SoC.
Note: Location is negotiable.

Possible locations could be Phoenix, San Jose, San Francisco, and possibly remote

Job Description
*

• Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, floor plan, place route, static timing analysis, IR Drop, EM, physical verification in advanced technology node
• Resolve design flow issues related to physical design, identify potential solutions, drive execution
• Deliver physical design of an end to end IP or integration of ASIC SoC design

Basic Qualifications:

• Minimum of 1 - 3 years of experience in any of the following:

• RTL2GDSIIon advanced technology nodes (7nm and below)
• Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.
• Block-level and Full-chip floor-planning and power grid planning.
• Python, TCL, or Perl programming.
• EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus or Calibre

• Bachelor’s Degree or equivalent work experience (12 years) or an Associate’s Degree with 6 years of work experience.

Preferred Qualifications:

• Experience running physical aware logic synthesis and achieving optimal synthesis QoR on low power designs
• Knowledge of static timing analysis and concepts, defining timing constraints exceptions, corners voltage definitions
• Experience with custom or regular clock tree synthesis implementation at block level or top level, clock power reduction techniques

Job Types: Full-time, Contract

Pay: $82,159.00 - $944,961.00 per year

Schedule:

• 8 hour shift
• Monday to Friday

COVID-19 considerations:
100% Remote due to COVID-19

Application Question(s):

• What is your work authorization?
• What is the hourly pay rate you are looking for? ($)

Education:

• Bachelor's (Preferred)

Experience:

• Physical Design Engineering: 3 years (Preferred)
• Block-level and Full-chip integration: 3 years (Preferred)
• EDA tools like DC/Genus, ICC2/Innovus, Primetime: 3 years (Preferred)
• RTL2Gate on advanced technology nodes (7nm and below): 3 years (Preferred)

Contract Length:

• More than 1 year
• Varies

Contract Renewal:

• Likely

Full Time Opportunity:

• Yes

Work Location:

• Multiple locations

Company's website:

• www.taasolutions.net

Work Remotely:

• Yes

COVID-19 Precaution(s):

• Remote interview process
• Social distancing guidelines in place