Design Verification Engineer In Sunnyvale CA

6 months contract

Title: Design Verification Engineer

Roles & Responsibilities:

• Responsibilities includes starting from test planning to closing verification using coverage metrics.
• Involves test bench development from scratch or modification to existing test bench infrastructure for verifying new features.
• Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model.
• Directed/constrained random test generation, failure analysis and resolution, coverage analysis.
• Debugging failures, bug tracking, and analyze and close coverage.

Skills, Experience, Education, & Training:

• Advanced knowledge of HVL methodology (UVM).
• Expertise in HVL and HDL (System Verilog, Verilog).
• Experience defining coverage space and writing coverage model.
• Experience with System Verilog Assertion (SVA) is a plus.
• Team player with excellent communication skills and the desire to take on diverse challenges.
• Experience writing scripts in languages such as Perl/Python.
• Solid verification skills in problem solving, constrained random testing, and debugging.
• Experience with Veloce or other HW accelerators and Formal is a plus.

Job Type: Contract

Pay: $60.00 per hour

Schedule:

• 8 hour shift

Ability to commute/relocate:

• Sunnyvale, CA: Reliably commute or planning to relocate before starting work (Required)

Work Location: One location